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Preliminary
M61541FP
6ch Electronic Volume with Tone Control
REJ03F0122-0100 Rev.1.0 Sep 09, 2004
Description
M61541FP is an audio signal processor for home audio. This IC contains 6 channel electronic volume and 2 band tone control.
Features
* Electronic Volume * Gain Control * Tone Control 6 channel independent Electronic Volume with High Voltage Transistor. (0 to -99dB/1dBstep, -dB) 6 channel independent Gain Control (0, 6, 12, 18dB) Bass: -14 to + 14dB(2dB step), Treble: -14 to + 14dB(2dB step)
Recommended Operating Condition
Supply Voltage Range AVCC = 7.0V(typ), AVEE = -7.0V(typ), DVDD = 3.0 to 5.5V
Application
* Receiver, AV Amp, Mini Stereo etc.
System Block Diagram
Lch Tone RchTone CLOCK DATA MCU I/F Gain Control Lout
Tone Lin Rin Volume Bass& Treble Bass& Treble
Volume
Gain Control
Rout
Cin SWin SLin SRin
Volume Volume Volume Volume
Gain Control Gain Control Gain Control Gain Control
Cout SWout SLout SRout
VOL GND
DGND
DVDD AVEE AVCC GND
Rev.1.0 Sep 09, 2004 page 1 of 15
M61541FP
Preliminary
Block Diagram and Pin Configuration
CL OCK DGND DA TA DV DD ROUT COUT SWOUT BA SR1 BA SR2 L OUT
20
19
18
Gain Control
17
16
15
14
13
DVDD
12
11
Gain Control +
-
MCU I/F
BASL2 21
+
-
10 SLOUT 9 SROUT
Bass /Tre
Gain Control Gain Control Gain Control Gain Control
BASL1 22 TRER 23 TREL 24 AGND 25
25k Lch Vol
8 AGND
+ + + +
-
Bass /Tre
7 SRIN
25k Rch Vol 25k 25k 25k 25k Cch Vol SWch Vol SLch Vol SRch Vol
6 SLIN Logic 5 SWIN 4 CIN
N.C. 3 N.C N.C. 2 N.C
INR 26 INL 27 N.C 28 N.C. N.C 29 N.C. N.C 30 N.C.
N.C. N.C. N.C. N.C. N.C. N.C.
AVCC AVEE
1 AGND
N.C.
31
N.C
32
A GND
33
N.C
34
N.C
35
N.C
36
N.C
37
A V CC
38
A V EE
39
N.C
40
N.C
Rev.1.0 Sep 09, 2004 page 2 of 15
M61541FP
Preliminary
Pin Description
Pin No. 1, 8, 25, 32 2, 3, 28, 29, 30, 31, 33, 34, 35, 36, 39, 40 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19, 20 21, 22 23 24 26 27 37 38 Pin Name AGND NC CIN SWIN SLIN SRIN SROUT SLOUT SWOUT COUT DVDD DATA CLOCK DGND ROUT LOUT BASR1, BASR2 BASL1, BASL2 TRER TREL RIN LIN AVCC AVEE Analog Ground NC Input pin of C channel Input pin of SW channel Input pin of SL channel Input pin of SR channel Output pin of SR channel Output pin of SL channel Output pin of SW channel Output pin of C channel Power supply to internal logic circuit Input pin of control data Input pin of control clock Ground of internal logic circuit Output pin of R channel Output pin of L channel Frequency characteristic setting pin of R channel tone control (BASS) Frequency characteristic setting pin of L channel tone control (BASS) Frequency characteristic setting pin of R channel tone control (Treble) Frequency characteristic setting pin of L channel tone control (Treble) Input pin of R channel Input pin of L channel Positive power supply to internal analog circuit Negative power supply to internal analog circuit Function
Rev.1.0 Sep 09, 2004 page 3 of 15
M61541FP
Preliminary
Absolute Maximum Ratings
Parameter Power Supply Power dissipation Thermal derating Operating temperature Storage temperature Note: AVEEDGND25C
THERMAL DERATINGS (MAXIMUM RATING) 2.0
POWER DI SSI PA TI ON pd (W)
1.5
1.46W
1.0
0.88
0.5
0 0 25 50 75 100 125 150
AMBIENT TEMPERATURE Ta ( C )
Recommended Operating Conditions
(Ta=25C, unless otherwise noted.)
Parameter Analog Supply Voltage (Positive) Analog Supply Voltage (Negative) Digital Supply Voltage Logic "H" level Input Voltage Symbol AVCC AVEE DVDD VIH Min 4.5 -7.5 3.0 DVDDx0.7 DGND Typ 7.0 -7.0 3.3 Max 7.5 -4.5 5.5 DVDD DVDDx0.2 Unit V V V V V DGND reference DGND reference Condition
Logic "L" level Input Voltage VIL Note: AVEEDGNDRev.1.0 Sep 09, 2004 page 4 of 15
M61541FP
Preliminary
Relationship Between Data and Clock
Data signal is read at the rising edge of CLOCK. Make "H" at the timing which DATA of D0-D23 make latch.
DATA
D0
D1
D2
D3
D21
D22
D23
CLOCK
When DATA is "H", latch signal is created at the falling edge of CLOCK. When CLOCK is "L" and latch signal is created, latch signal is read at the falling edge of DATA.
Clock and Data Timings
DATA
(D0 to D23)
t cr
LATCH
75% 25% tSLD
tSLD tHLD tSHD tHHD
tHLD tSC
75% 50% 25%
CLOCK
tr tWHC
tf tWLC
Timing Definition of Digital Block
Parameter CLOCK cycle time CLOCK pulse width ("H" level) CLOCK pulse width ("L" level) Rising time of clock and data Falling time of clock and data DATA setup time (Rising time of clock) DATA setup time (Falling time of clock) DATA hold time ("H" level) DATA hold time ("L" level) CLOCK setup time Symbol tcr tWHC tWLC tr tf tSHD tSLD tHHD tHLD tSC Min 8 3.2 3.2 1.6 1.6 1.6 1.6 1.6 Limits Typ Max 0.8 0.8 s Unit
Rev.1.0 Sep 09, 2004 page 5 of 15
M61541FP
Preliminary
Power on Reset
This IC built-in the power on reset function. The voltage of DVDD (13 pin) -DGND (16 pin) less than 2.6V, the serial DATA can not accept.
DVDD(13pin) - DGND(16pin)
(V)
2.6 V
(S) Reset time After reset is canceled, the serial DATA can accept.
Release of reset.
Note:
AVEEDGNDData Control Specification
Initialize all data of the 4 formats when Digital Power supply (DVDD) turns on. Prohibit using except specified Data code as follows.
Slot1
D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14a D15a D16a D17a D18a D19a D20a D21a D22 D23
1/0 1/0
1/0 1/0 1/0
1/0
1/0 1/0
(1) Bass/ Tone control Bypass
(2) Treble
0
0
0
0
0
0
0
0
Slot2
D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14b D15bD16b D17b D18b D19b D20b D21b D22 D23
(3) Lch Gain Control
(4)Lch Volume
(3) RchGain Control
(4)Rch Volume
0
0
0
0
0
1
Slot3
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14c D15c D16c D17c D18c D19c D20c D21c D22 D23
(3) CchGain Control
(4)Cch Volume
(3) SWchGain Control
(4)SWchVolume
0
0
0
0
1
0
Slot4
D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10d D11d D12d D13d D14d D15d D16d D17d D18d D19d D20d D21d D22 D23
(3) SLch Gain Control
(4)SLchVolume
(3) SRchGain Control
(4)SRchVolume
0
0
0
0
1
1
Note:
No guarantee except for these codes.
Rev.1.0 Sep 09, 2004 page 6 of 15
M61541FP
Preliminary
Setting Code
It's initial setting when power is turned on. (1) Bass/Bypass (Tone control is bypass)
ATT Setting +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB D8a 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 D9a 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 D10a 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 D11a 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
(2) Treble
ATT Setting +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB D12a 1 1 1 1 1 1 1 1/0 0 0 0 0 0 0 0 D13a 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 D14a 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 D15a 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bypass* 0 * Tone control is bypass.
(3) Gain Control
Lch Rch ATT Setting Cch SWch SLch SRch 0dB 6dB 12dB 18dB D0b D9b D0c D9c D0d D9d 0 0 1 1 D1b D10b D1c D10c D1d D10d 0 1 0 1
Rev.1.0 Sep 09, 2004 page 7 of 15
M61541FP (4) 6channel Volume
Preliminary
It's initial setting when power is turned on.
Lch Rch Cch SWch SLch SRch 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB -28dB -29dB -30dB -31dB -32dB -33dB -34dB -35dB -36dB -37dB -38dB -39dB -40dB -41dB -42dB -43dB D2b D11b D2c D11c D2d D11d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3b D12b D3c D12c D3d D12d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D4b D13b D4c D13c D4d D13d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D5b D14b D5c D14c D5d D14d 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 D6b D15b D6c D15c D6d D15d 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D7b D16b D7c D16c D7d D16d 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D8b D17b D8c D17c D8d D17d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ATT
Rev.1.0 Sep 09, 2004 page 8 of 15
M61541FP
Lch Rch Cch SWch SLch D2b D11b D2c D11c D2d D11d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3b D12b D3c D12c D3d D12d 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4b D13b D4c D13c D4d D13d 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 D5b D14b D5c D14c D5d D14d 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 D6b D15b D6c D15c D6d D15d 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 D7b D16b D7c D16c D7d D16d 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D8b D17b D8c D17c D8d D17d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Preliminary
ATT
SRch -44dB -45dB -46dB -47dB -48dB -49dB -50dB -51dB -52dB -53dB -54dB -55dB -56dB -57dB -58dB -59dB -60dB -61dB -62dB -63dB -64dB -65dB -66dB -67dB -68dB -69dB -70dB -71dB -72dB -73dB -74dB -75dB -76dB -77dB -78dB -79dB -80dB -81dB -82dB -83dB -84dB -85dB -86dB -87dB -88dB -89dB -90dB
Rev.1.0 Sep 09, 2004 page 9 of 15
M61541FP
Lch Rch Cch SWch SLch D2b D11b D2c D11c D2d D11d 1 1 1 1 1 1 1 1 1 D3b D12b D3c D12c D3d D12d 0 0 0 0 0 1 1 1 1 D4b D13b D4c D13c D4d D13d 1 1 1 1 1 0 0 0 0 D5b D14b D5c D14c D5d D14d 1 1 1 1 1 0 0 0 0 1/0 D6b D15b D6c D15c D6d D15d 0 1 1 1 1 0 0 0 0 1 D7b D16b D7c D16c D7d D16d 1 0 0 1 1 0 0 1 1 1/0 D8b D17b D8c D17c D8d D17d 1 0 1 0 1 0 1 0 1 1/0
Preliminary
ATT
SRch -91dB -92dB -93dB -94dB -95dB -96dB -97dB -98dB -99dB
-dB 1 1 1/0 Note: No guarantee except for these codes.
Electrical Characteristics
(Unless otherwise noted, Ta = 25C, AVCC = 7V, AVEE = -7V, DVDD = 5V, f = 1kHz, Volume = 0dB, Gain Control = 0dB, Tone = Bypass) (1) Power supply characteristics
Limits Parameter Analog positive power circuit current Analog negative power circuit current Digital power circuit current Symbol AIcc AIee DIdd Min -42 Typ 32 -32 2 Max 42 3 Unit mA mA mA Test condition With AVCC = 7V and AVEE = -7V 37pin current, when no signal is provided With AVCC = 7V and AVEE = -7V 38pin current, when no signal is provided With DVDD = 3.3V, 13pin current, when no signal is provided
Rev.1.0 Sep 09, 2004 page 10 of 15
M61541FP (2) Input/Output characteristics (OVER ALL)
Limits Parameter Input resistance Maximum output voltage Pass gain Symbol Min Rin 17 VOM Gv 3.8 -2.0 -- -0.5 -- Typ 25 4.4 0 Max 33 -- 2.0 Unit k Vrms dB % dB 4 to 7,26,27 pin Test condition
Preliminary
4 to 7,26,27pin input, 9 to 12,17,18pin output, THD = 1%, RL = 10k, Output Gain Control = +6dB 4 to 7,26,27pin input, 9 to 12,17,18pin output, Vi = 0.3Vrms, FLAT 4 to 7,26,27pin input, 9 to 12,17,18pin output, BW: 400Hz to 30kHz, f = 1kHz, Vo = 0.5Vrms, RL = 10k 26,27pin input, 17,18pin output, Vi = 0.5Vrms, JIS-A JIS-A, Rg = 0, 17,18pin output, Volume = -dB setting Output Gain Control = 0dB Output Gain Control = +12dB Output Gain Control = 0dB Output Gain Control = +12dB
Total harmonic THD distortion Balance of CBAL mutual channels Vono1 Output noise voltage Vono2 Vono3 Channel separation CS
0.0008 0.008 0 0.9 4.5 1 5 1 5 -90 0.5 3 15 3 15 3 15 -70
Vrms
JIS-A, Rg = 0, 17,18pin output, Volume = 0dB setting
JIS-A, Rg = 0, 9 to 12pin output, Output Gain Control = 0dB Volume = 0dB setting Output Gain Control = +12dB dB Vo = 1Vrms, Rg = 0, RL = 10k, JIS-A
(3) 6 channel Volume characteristics
Limits Parameter Maximum attenuation Volume gain gang error of mutual channels Symbol ATTmax Dvol Min Typ Max -- -100 -95 -0.5 0 +0.5 Unit dB dB Test condition Vi = 2Vrms, JIS-A, VOL = -dB Volume = 0dB
(4) Tone control characteristics (Unless otherwise noted, Tone ON/OFF = ON)
Limits Parameter Tone control voltage gain (Boost/Bass) Tone control voltage gain (Cut/Bass) Tone control voltage gain (Boost/Treble) Tone control voltage gain (Cut/Treble) Balance of mutual channels Symbol G (BASS) B G (BASS) C G (TRE) B G (TRE) C BALT Min +12 -16 +12 -16 -2 Typ +14 -14 +14 -14 0 Max +16 -12 +16 -12 +2 Unit dB dB dB dB dB Test condition f = 100Hz Bass +14dB setting f = 100Hz Bass -14dB setting f = 10kHz Treble +14dB setting f = 10kHz Treble -10dB setting Bass setting +14, -14dB Treble setting +14, -14dB
Rev.1.0 Sep 09, 2004 page 11 of 15
M61541FP
Preliminary
Tone Control
(1) Bass
< Boost >
IN
+ R3 R2 f0 =
+
OUT
[Designed Parameter] R1=4.7k, C1=0.047F, C2=0.15F Gain Setting (Hz) +14dB +12dB +10dB +8dB +6dB +4dB +2dB (dB)
Designed Parameter
1 2 R1(R2+R3)C1C2 (R2+R3)R1C1C2
C1 0.047 R1 4.7K
C2 0.15
Q=
R1(C1+C2)+R3C1 R1(C1+C2)+(R2+R3)C1 R1(C1+C2)+R3C1
R3(k ) R2(k ) 0.19 79.81 5.21 74.66 11.83 68.17 19.99 60.01 30.27 49.73 43.21 36.79 59.49 20.51
Gv = 20 log
< Cut >
IN
+ R2
+
R3 [Designed Parameter] R1=4.7k , C1=0.047F , C2=0.15F C2 0.15 (Hz) C1 0.047 R1 4.7K Gain Setting -14dB -12dB -10dB -8dB -6dB -4dB -2dB
Designed Parameter
OUT
R2(k ) 79.81 74.66 68.17 60.01 49.73 36.79 20.51
f0 =
1 2 R1(R2+R3)C1C2 (R2+R3)R1C1C2
Q=
R1(C1+C2)+R3C1 R1(C1+C2)+R3C1 R1(C1+C2)+(R2+R3)C1
R3(k ) 0.19 5.21 11.83 19.99 30.27 43.21 59.49
Gv = 20 log
(dB)
Rev.1.0 Sep 09, 2004 page 12 of 15
M61541FP (2) Treble
Preliminary
< Boost >
IN
+ R5 R4
+
[Designed Parameter] RC=0.022F
OUT
Gain Setting +14dB +12dB +10dB +8dB +6dB +4dB +2dB
Designed Parameter
Gv =20 log
0.022
(R4+R5)2+ RC2 R4 +RC
2 2
(dB)
R4(k ) R5(k ) 1.03 5.23 1.41 4.85 1.86 4.40 2.40 3.86 3.06 3.20 3.90 2.36 4.95 1.31
RC

IN
Gv =20 log
R4 +RC
2
2
2
(dB)
2
+
R5
(R4+R5) + RC
-
[Designed Parameter] RC=0.022F
+
OUT
Gain Setting -14dB -12dB -10dB -8dB -6dB -4dB -2dB
Designed Parameter
R4
RC
0.022
R5(k ) 5.23 4.85 4.40 3.86 3.20 2.36 1.31
R4(k ) 1.03 1.41 1.86 2.40 3.06 3.90 4.95
Curve of characteristics
Tone gain Gv (dB)
Frequency f(Hz)
Rev.1.0 Sep 09, 2004 page 13 of 15
M61541FP
Preliminary
Application Example
L
4.7k 0.047
R
DVDD 3.3V
C
SW
0.15
4.7
4.7
MCU
16 15 14
+ 100 0.1
4.7
4.7
20
19
+ 18
Gain Control
+ 17
13
DVDD
+ 12
+ 11
4.7
Gain Control +
-
MCU I/F
SL
0.047 4.7k 0.15 0.022
21
+
-
10 9
Bass /Tre
Gain Control Gain Control Gain Control Gain Control
+
4.7
SR
22 23
+
8
+ + + + 2.2
-
0.022
+
24 25
2.2
Bass /Tre
7
25k Rch Vol 25k 25k 25k 25k Cch Vol SWch Vol SLch Vol SRch Vol 2.2
SRIN
+
6
25k Lch Vol
SLIN
Logic
5 4
2.2
+
+
RIN LIN
26 27
50k
SWIN
2.2
2.2
+
N.C. 28 N.C. N.C. 29 N.C. N.C. 30 N.C.
N.C. N.C. N.C. N.C. N.C. N.C.
AVCC AVEE
31
N.C.
32
33
N.C.
34
N.C.
35
N.C.
36
N.C.
+
37
38
39
N.C.
40
N.C.
+ 100 0.1 100 0.1
AVCC AVEE 7V -7V
Rev.1.0 Sep 09, 2004 page 14 of 15
N.C.
+
CIN
50k
N.C. 3 N.C. N.C. 2 N.C.
1
M61541FP
Preliminary
Package Dimensions
JEITA Package Code P-LQFP40-7x7-0.65 RENESAS Code PLQP0040JB-A Previous Code FP-40B MASS[Typ.] 0.2g
HD
*1
D 21
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
30
31
20 bp b1
Reference Symbol
Dimension in Millimeters Min Nom 7.0 7.0 1.40 8.8 8.8 9.0 9.0 9.2 9.2 1.70 0.08 0.20 0.13 0.25 0.22 0.12 0.17 0.15 0 0.65 0.13 0.10 0.575 0.575 0.40 0.50 1.0 0.60 8 0.22 0.22 0.30 Max
c1
HE
E
c
D E A2
*2
ZE
Terminal cross section
HD HE A A1 bp
40
11
1 ZD Index mark
10 F
b1 c
A
A2
c
c1
A1
L L1
e x y ZD ZE L L1
Detail F
e
*3
bp y
x
M
Rev.1.0 Sep 09, 2004 page 15 of 15
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
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